发明名称 CHECK SYSTEM FOR DATA LINE EXCHANGE
摘要 PURPOSE:To check the normaliy of a data line exchange, by monitoring the normality of a parallel synchronizing operation, in a duplex data line exchange which mutually exchanges and controls a plurality of data lines in time division multiplex. CONSTITUTION:Data inputted from data lines L00-Lnm are multiplexed at data multiplex processors MX0-MXn and transmitted to data line exchanges LSW0 and LSW1 at the same time. The data transmitted from the processors MX0- MXn are stored in buffer memories BM0-BMn. The data read out from the buffer memories are transmitted to a processor of a line to be connected via spatial switches G00-Gnn. An output operating circuit PG performs a prescribed operation for an output of each processor and outputs the result to a collating circuit MAT. When both exchanges LSW0 and LSW1 are normal, the coincidence is detected at the device MAT, and if failed, the disidence is detected and an error signal is transmitted to a processor CPU.
申请公布号 JPS5857843(A) 申请公布日期 1983.04.06
申请号 JP19810155525 申请日期 1981.09.30
申请人 FUJITSU KK 发明人 CHINO MAMORU;HIWATARI SANEYUKI;NISHIBASHI TETSUO;KUSUMOTO TOMIHISA
分类号 H04L12/54;(IPC1-7):04L11/20 主分类号 H04L12/54
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