| 摘要 |
PURPOSE:To accurately pick up a timing signal, by eliminating unnecessary frequency component due to consecutive ''1'' or ''0'' in an input data based on a phase lock of a PLL in a digital signal transmission. CONSTITUTION:A transmission code consists of a bit synchronism X a frame synchronism Y and information Z, and the bit synchronism part X at the data transmission is taken as a repetitive signal of ''1'', ''0'', ''1'', ''0'' to avoid the generation of double frequency component. The number of bits of the synchronism part X and the phase lock time of a PLL circuit 7 are set so that the phase lock of the PLL circuit 7 at the part X can be completed. After the completion of the phase lock is detected at a coincidence circuit 12, unnecessary double frequency component generated at the frame synchronism Y and the information Z are masked for removal based on an output signal F of the PLL circuit 7. |
