发明名称 TIMER CIRCUIT
摘要 PURPOSE:To accurately and easily set time, by assembling two stages of inverters having a suitable ratio between the 1st capacitor and the inverter input terminal and increasing the voltage of the 1st capacitor. CONSTITUTION:A potential change of a capaitor CL is received at an offset circuit 20 consisting of two stages of inverters comprising transistors Q8-Q11. Then, taking around 1V of the threshold voltage of an output inverter and a linear region of discharge characteristic of a charge pump up to about 2V into consideration, the timer set time accuracy can be increased by using this region only. Thus, the inverting amplification of the inverter is applied, the offset amplifier consisting of the two stages of the inverters is constituted without losing the logic and the ratio of the inverters is set to a suitable value, allowing to easily correct the deviation from the threshold value of the output inverter.
申请公布号 JPS5848527(A) 申请公布日期 1983.03.22
申请号 JP19810147400 申请日期 1981.09.18
申请人 NIPPON DENKI KK 发明人 KOBAYASHI SATORU
分类号 G11C11/407;H03K17/28;H03K17/284 主分类号 G11C11/407
代理机构 代理人
主权项
地址