| 摘要 |
PURPOSE:To raise the integration density by suppressing latch-up through deepened junction of the diffusion layers for ohmic contact of the power source terminal to the substrate and well layer and by eliminating necessity of making large the interval between the source and drain of MIS FET formed on the substrate and well. CONSTITUTION:Latch-up can be suppressed because the base resistance R1 of lateral P-N-P transistor Tr1 and the base resistance R3 of vertical N-P-N transistor Tr2 can be reduced by deepening the junction of the N<+> diffusion layer 32 and P<+> diffusion layer 21 for the ohmic contact. When R1 is reduced, the base voltage of Tr1 is more stabilized and when R3 is reduced, the base voltage of Tr2 is stabilized and thereby generation of positive feedback loop can be suppressed. When any one of the base resistances R1 and R2 is reduced, a resultant suppression effect can be obtained. |
