| 摘要 |
PURPOSE:To reduce the output waveform distortion due to switching and simplify the circuit constitution to reduce the cost, by using a ladder-type decoding circuit as a resistance ladder circuit. CONSTITUTION:A composite signal C(t) supplied to an input terminal IN is subjected to impedance conversion through an operational amplifier OP1 and is supplied to reference input terminals T0 of two ladder-type decoding circuits LAD1 and LAD2. The 19kHz pilot signal extracted from the signal C is applied to a PLL circuit 14, and a 532kHz clock signal is applied to a timing signal generating circuit 15. Analog switches S1-S3 of circuits LAD1 and LAD2 are switched by the output of the circuit 15, and the product between the signal C(t) and a signal where the voltage is changed stepwise is obtained in an output terminal T4, and left and right signals are obtained through operational amplifiers OP2 and OP3. |
