发明名称 Method of and circuit arrangement for automatic signal-level control
摘要 A binary input signal S multiplied by a level-controlling modifier Xn-1 is periodically sampled to determine its amplitude whose value is then differentially combined with a fixed reference value R to produce an error signal. The latter is multiplied by the same modifier Xn-1 and by a fractional coefficient k to yield a corrective value which is then algebraically combined with modifier Xn-1 to produce an updated modifier Xn for the next sampling cycle. To avoid instability, the modified input signal may be subjected to a limitation of its dynamic range before or after sampling. A load to be driven by the input signals may receive the modified signal itself or the modifier used to control its level.
申请公布号 US4370725(A) 申请公布日期 1983.01.25
申请号 US19800188036 申请日期 1980.09.17
申请人 CSELT - CENTRO STUDI E LABORATORI TELECOMUNICAZIONI S.P.A. 发明人 DI TRIA, PAOLO
分类号 H03G3/20;(IPC1-7):H04L15/24 主分类号 H03G3/20
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