| 摘要 |
PURPOSE:To obtain a delay lock loop with an improve S/N ratio by dividing tap outputs of a received signal delay line into a preceding and a trailing group, and corelating these groups each other, and then obtaining a maximum output when all tap outputs are synthesized. CONSTITUTION:An M-series signal of a carrier band after two-phase phase modulation is inputted to a receiving terminal 102, and delayed through a delay line 200 with taps by one chip for every tap. On the other hand, an M-series generator 270 generates the same series as the signal series of a diffusion code generator on a transmission side, and the output and respective tap outputs of the delay line 200 are inputted to correlators 211-215. The outputs of the correlators 211-213 are summed up by an adder 220, and outputs of the correlators 214 and 215 are also summed up by an adder 230. The difference between the outputs of both the adders is outputted from a subtracter 240 and smoothed by a loop filter 250 to control a voltage-controlled oscillator 260 by its output, thereby supplying the output of the oscillator as a clock signal for the M-series generator 270. |
