| 摘要 |
A delta frame circuit is disclosed. The delta frame circuit is connected to the video output of, for example, an imaging system for the purpose of producing a moving target indication radar or, for example, a chopped imaging system for the purpose of removing fixed pattern or undesirable offset voltages. The delta frame circuit comprises a plurality of capacitors having top plates connected to the video output and lower plates connected to the drains of a first plurality of field effect transistors. The gates and sources of these field effect transistors are connected, respectively, to a Y address circuit and drains of a second plurality of field effect transistors. The gates and sources of these field effect transistors are connected, respectively, to a X address circuit and to the drains of a third plurality of field effect transistors whose gates and sources are connected, respectively, to the Y address circuit, and junction of a precharge reference voltage and output amplifier. The X and Y address circuits address the capacitors which store the video output of a field pixel by pixel for comparison to a reference voltage and a second video field whereby the offset signals are substantially removed. |
