| 摘要 |
PURPOSE:To make the control voltage delay time characteristic of a delay circuit comprising multi-stage connection of CMOS circuits by comparing an output signal of a phase comparator with a control signal and supplying its comparison output voltage to the delay circuit as a power voltage. CONSTITUTION:A 1st delay circuit 1 acts like a main delay circuit, a 2nd delay circuit 6 acts like a control delay circuit, a 3rd delay circuit 11 functions an offset delay circuit and a 4th delay circuit 12 acts like a standard monitor delay circuit respectively. Then the phase of the standard monitor output is compared with the phase of the control delay circuit to absorb the variance in a CMOS inverter 2. Thus, the characteristic of Vc1 versus VM is made linear while the absolute value of the delay time TM of the delay circuit 1 is in variance, the variance in the CMOS inverter 2 is absorbed largely, thereby the connection stage number is reduced remarkably. Moreover, the control range of the delay time TM of the delay circuit 1 is minimized among control ranges restricted by various factors having variance. |
