发明名称 NEGATIVE RESISTANCE CIRCUIT
摘要 <p>PURPOSE:To obtain a circuit showing a negative resistance, by suitably connecting two transistors (TR) for FETs such a MOS TRs. CONSTITUTION:A terminal 25 of a P-FET22 an a drain 19 of an N-FET 17, and a terminal 20 of the N-FET17 and a drain 24 of the P-FET22 are respectively connected. To a gate 26 of the FET22, a voltage between a threshold voltage of the FET22 when a substrate potential is the same as the source potential to the voltage at the source terminal 23 of the FET22 and a threshold voltage of the FET22 when the substrate potential is lower than the source potential is applied, and to a gate 21 of the FET17, a voltage between a threshold voltage of the FET17 when the substrate potential is the same as the source potential to the voltage at the source 18 of the FET17 and a threshold voltage of the FET17 when the substrate potential is higher than the source voltage is applied. Thus, a negative resistance circuit is obtained.</p>
申请公布号 JPS57207413(A) 申请公布日期 1982.12.20
申请号 JP19810093160 申请日期 1981.06.17
申请人 NIPPON DENKI KK 发明人 OONO YASUO
分类号 H01L29/86;H03H11/52 主分类号 H01L29/86
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