发明名称 PLURAL OPERATION SEQUENCE GENERATING SYSTEM IN NUMERICAL CONTROL DEVICE
摘要 PURPOSE:To simplify the understanding of a program by using address information consisting of >=2 characters to which a character indicating the operation sequency number to be related to a data is added as an address character. CONSTITUTION:Plural expansion subprograms are registered in a memory 1a. An address information discriminating circuit 12 discriminates between address information consisting of a normal character and that consisting of >=2 characters and transfers these address information to an one-character address decoder 4 and a plural-character address decoder 13 respectively. The address information decoded by the >=2 character address decoder 13 is inputted to a data word register group 14. An NC data analyzer 8 analyzes command data of the register groups 6, 14. A subprogram controlling device 9 selectes an expansion subprogram to be executed.
申请公布号 JPS57201903(A) 申请公布日期 1982.12.10
申请号 JP19810006649 申请日期 1981.01.20
申请人 OKUMA TEKKOSHO KK 发明人 FUKAYA YASUSHI;RIYOUKI MASATO;ISHIHARA TOSHIO
分类号 G05B19/4155;G05B19/408 主分类号 G05B19/4155
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