Multimode memory system using a multiword common bus for double word and single word transfer

摘要

A memory subsystem couples to a double wide word bus in common with a number of central processing units for processing memory requests received therefrom. The subsystem includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes common control circuits, timing circuits and common addressing circuits. The addressing circuits which couple to both module units provide the required address signals to both modules for enabling the simultaneous access of a pair of words therefrom into a pair of data registers. The outputs of the data registers couple to the inputs of a pair of output multiplexer circuits. The outputs of the multiplexer circuits are connected to provide double wide output to the double wide word bus. The timing circuits generate a sequence of timing signals for access and read out of the pair of words into the data registers for simultaneous transfer via the multiplexer circuits to the double wide bus. The control circuits which in response to each memory request specifying a double fetch operation, condition the multiplexer circuits and memory subsystem for operation in a degraded mode. When in this mode, the pair of words read out to the data registers are multiplexed onto a portion of the bus for transfer to the requesting central processing unit over a corresponding number of successive bus cycles thereby making the memory subsystem compatible with central processing units having a double fetch capability.