Equaliser system for equalising transit-time fluctuations and fixed frame displacements

摘要

This equalisation of transit-time fluctuations and fixed frame displacements is achieved by the fact that the simultaneous equalisation of the transit-time fluctuations and fixed frame displacements is effected by an information store (SP3) which is used as buffer and which allows a displacement of the loading and reading-out of the information bits within a wide range. The clock phases of the information bits in each case to be loaded and to be read out pass in opposite directions through this information store (SP3). Figure 3 shows the block diagram for the equaliser system (A1...An). The input to the equaliser system (A1...An) is formed by an 8-bit serial/parallel converter (SPW1) into which the input bit streams (I'1...I'n) are loaded and thus divided into packets of 8 bits. <IMAGE>