Synchronous binary-counter and programmable rate divider circuit

摘要

An MOS parallel carry synchronous binary counter/clock rate divider circuit has a chain of simultaneously clocked T flip-flop interconnected by an improved enable logic circuit having a plurality of identical carry stages each associated with a different flip-flop except the first and last flip-flop of the chain. Each carry stage has an input terminal connected to the inverted enable input of its associated flip-flop, an output terminal connected to the inverted enable input of the next flip-flop in the chain, a transmission gate transistor having a conduction channel connected in series between the input and output terminals and a gate connected to the normal output of the associated flip-flop, and a depletion mode load transistor having a conduction channel connected between a VDD power supply terminal and the output terminal and a gate connected to the output terminal. The carry stage associated with the first flip-flop comprises an inverter having an input connected to the normal output of the first flip-flop and an output connected to the inverted enable input of the second flip-flop. The clock rate division signal provided by the output of the last flip-flop in the chain can be made programmable by including a programming network in each carry stage. The programming network comprises one or more transistors having conduction channels coupled in series between the output terminal and ground and having gates responsive to control signals for forcing a logic "0" level on the output terminal.