发明名称 |
Duty cycle correction circuit and delay locked loop having the same |
摘要 |
A duty cycle correction (DCC) circuit including first and second clock dividers for dividing ordinary and sub-input clocks. Optional first and second variable delay devices delay the divided clocks. First and second mixers mix an optionally delayed ordinary divided clock and sub-ordinary divided clock, or an ordinary divided clock and an optionally delayed sub-ordinary divided clock. A logic combination device is included to produce a clock at the same frequency as the ordinary and sub-input clocks, with a corrected duty cycle.
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申请公布号 |
US6859081(B2) |
申请公布日期 |
2005.02.22 |
申请号 |
US20030638994 |
申请日期 |
2003.08.11 |
申请人 |
HYNIX SEMICONDUCTOR INC. |
发明人 |
HONG SANG-HOON;KIM SE-JUN;KOOK JEONG-HOON |
分类号 |
H03L7/08;H03K5/156;H03L7/081;H03L7/089;(IPC1-7):H03K3/017 |
主分类号 |
H03L7/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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