发明名称 PSEUDO ERROR PULSE INSERTING CIRCUIT
摘要 PURPOSE:To achieve adjustment and test only with a transmission and reception data processing section, by inserting a pseudo random pulse having no correlation to data. CONSTITUTION:After a clock signal is frequency-divided at a frequency divider 2, a pseudo random pattern generator 3 is driven. A pseudo random pattern for input data series is picked up from outputs T0-Tn-1 of each stage of an N stage pseudo random pattern generator 3. The pseudo random pattern is inserted to a dta train via an exclusive logical sum 5. As a result, the polarity of data of the same time slot as the pseudo error pulse is inverted. This inverted part becomes the data error. The data error rate is determined by adjusting the frequency dividing ratio of the frequency divider 2.
申请公布号 JPS57174958(A) 申请公布日期 1982.10.27
申请号 JP19810060949 申请日期 1981.04.21
申请人 NIPPON DENKI KK 发明人 SUEMITSU TAKAHIRO;YANAGISAWA TAKASHI
分类号 H04L1/24;H04L27/00 主分类号 H04L1/24
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