发明名称 |
Split phase delay equalizer with reduced insertion loss |
摘要 |
A split phase delay equalizer is provided which reduces loss without resorting to high values of load impedance. The equalizer has a pair of parallel circuit branches, one of which is through the base and collector of a transistor, and the other through a reactance network connected between the collector and base of the transistor.
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申请公布号 |
US4356460(A) |
申请公布日期 |
1982.10.26 |
申请号 |
US19800214299 |
申请日期 |
1980.12.08 |
申请人 |
ROCKWELL INTERNATIONAL CORPORATION |
发明人 |
CUNNINGHAM, VERNON R. |
分类号 |
H04B3/14;(IPC1-7):H03H11/12 |
主分类号 |
H04B3/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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