| 摘要 |
PURPOSE:To increase the permissible range of level variation and jitters by detecting a block synchronizing signal by discriminating the combination order of the time length of the low-level state of a signal waveform and that of the high-level state. CONSTITUTION:Data Da supplied to an input terminal 30 is supplied to a part consisting of D type flip-flops 32 and 33, an EOR circuit 35, etc., to generate a pulse P1 at the time of variation. A clock having a period a tenth as long as a data readout period is supplied to a terminal 31. A counter 34 shows counting values which correspond to time intervals T1, T2- of the P1 because it is cleared by the P1. Those counting values are compared by comparators 41-45 with numerals in setting parts 36-40 showing the T1, T2- which correspond to block synchronizing signals, and their outputs are supplied to AND circuits 46-49. Further, they are connected to SR flip-flop circuits FF1-FF6 by using AND circuits 50-56. Then, block synchronism detection pulses appear at the terminal Q6 of the FF6. |
