| 摘要 |
PURPOSE:To realize the optional reading by an address designation given from a microprocessor, by using a counter that counts the synchronizing signals plus plural RAMs which store the synchronising signals with every bit and replacing the addresses successively with every unit data. CONSTITUTION:When the write control signal WR is applied to a terminal T3 from the muCPU side, a counter 1 works by the rise of the synchronizing signal SY. Then an AND gate 41 opens to designate an address A1 of storage elements 21-2n, and the data input signal DA is stored in a storage element 2 by the fall of the signal SY. The address of the element 2 is replaced by the counter 1 while the signal WR is applied to perform the writing of data successively. The control signal RE read out to a terminal T4 from the muCPU is applied to the address signal AD via terminals T51-T5n. Thus the contents of a memory 2 is read through a data output terminal DOU, AND gates 61-6n and terminals T61-T6n respectively. |
