发明名称 TESTING SYSTEM FOR INTEGRATED CIRCUIT ELEMENT
摘要 PURPOSE:To obtain an LSI testing system which tests the devices to be measured at optimum periods in follow up to the device characteristics by synchronizing the testing periods of input patterns with the response time of the devices to be measured or the delay time of internal elements. CONSTITUTION:An input pattern and an expectation pattern are transmitted from a pattern generating circuit 5, and the information for modulating the input pulses and expectation waveform is transmitted from a timing generating circuit 6. From these outputs, the input pulse waveform is made in an input pulse modulating circuit 4 and is applied to the input of a device 2 to be measured via a driver circuit 3. The output of the device 2 is converted to logical levels by voltage comparators 8, and these are compared with the expectation waveform by a coincidence detecting circuit 9. The comparison is carried out with all of the output pins, and when all the pins coincide, a signal is generated with a trigger signal generating circuit 11, and the waveform of the next pattern is formed. Thereby, the tests are carried out always optimum test periods in accordance with the variances in the devices to be measured.
申请公布号 JPS57169684(A) 申请公布日期 1982.10.19
申请号 JP19810055327 申请日期 1981.04.13
申请人 YAMAGATA NIPPON DENKI KK 发明人 MAKI MAMORU
分类号 G01R31/28;G01R31/317;G01R31/319 主分类号 G01R31/28
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