发明名称 |
SPEED CONTROLLER OF PCM RECORDER |
摘要 |
<p>PURPOSE:To prevent a wow and a flutter during a tape run by detecting the frequency variation of a write clock signal from variation in difference between the address counter output and read address counter output of a buffer memory. CONSTITUTION:The time-axis correction of a reproduced digital signal is carried out by a buffer memory 1; and a write address counter 2 performs counting by a write clock signal synchronized with a signal from a tape to specify a write address signal to the memory 1, and a read address counter 4 performs counting by a read clock signal 5 from a quartz oscillator, etc., to specify the read address of the memory 1. A difference between both the address is calculated by a subtracting circuit 6 and fed back to a capstan motor through a D/A converting circuit 7 to control a tape speed. Consequently, the evil influence of a wow and a flutter upon signal processing is removed by the simple constitution.</p> |
申请公布号 |
JPS57164465(A) |
申请公布日期 |
1982.10.09 |
申请号 |
JP19810049859 |
申请日期 |
1981.04.01 |
申请人 |
MATSUSHITA DENKI SANGYO KK |
发明人 |
KIHARA NOBUYOSHI;MATSUSHIMA KOUJI;TSUJI SHIROU;SHIMEKI TAIJI;KATOU MISAO |
分类号 |
G11B20/10;G11B15/46;G11B20/22 |
主分类号 |
G11B20/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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