| 摘要 |
PURPOSE:To quicken the point of time of output generation, by providing an RSFF with a frequecy division circuit of direct variable type and setting and resetting the RSFF before a half clock at the production of the final stage output. CONSTITUTION:Two-modulus frequency division output of 64-frequency division or 65-frequency division is obtained from a direct variable frequency divider A controllable for 8-frequency and 9-frequency division, and 8-frequency division frequency expander consisting of T type FFs T1, T2 and T3 and a frequency division ratio control output gate G. The gate G is possible to read a signal M if the 9-frequency division from the PLL is made or not, only when the output of the T type FFsT1-T3 is all at an L state. The RSFFT4 is set and reset before a half clock CP from the output of the FFT3 and supplies the output shifted by a half clock before the output of the FFT3 being the final output to the PLL. Thus, since the output of frequency division can be applied to the PLL earlier, the high speed operation of the PLL is not requested. |
