| 摘要 |
PURPOSE:To prevent reduction of the sectional area and disconnection of the lower layer wiring even when slipping of position is generated between the upper layer wiring and a connecting hole when patterning of the upper layer Al wiring is to be performed by a method wherein the upper face of the lower layer Al wiring is covered with a plasma Si film. CONSTITUTION:An Si substrate formed with the prescribed element region is covered with PSG19, and a connecting window is formed. The lower layer Al layers 20' are formed selectively, the surface thereof is covered with an interlayer insulating film 22 of PSG, and a connecting window 23 is formed. After the reflow treatment is performed on the window 23, the amorphous plasma Si layer 24 is piled up, and an Al layer 24 is laminated. When etching is performed using a resist mask 26 to form the upper layer Al wirings 25', the plasma Si film 24 prevents etching and removal of the lower layer Al wirings 20' completely, and reduction of quality of the lower layer wiring is not generated. When plasma etching is performed in CF4+O2 gas to form an opening 23 in the film 24, Al is scarcely etched. Finally, the resist mask 26 is removed and is covered with PSG27, heat treatment is performed in Ar gas, the plasma Si layer 24 is made to be diffused in the Al layers 25', 20', and the upper and the lower wiring layers are connected with low resistance to complete the multilayer wiring. |
