发明名称 OPERATION CONTROL SYSTEM FOR CENTRAL PROCESSING DEVICE OF COMPUTER
摘要 PURPOSE:To make it possible to perform always the reprocessing of instructions, by storing always contents of the first storage device in the second small-size and cheap storage device and returning contents of the second storage device to the first storage device to restore the state before the execution of instructions when an error occurs. CONSTITUTION:In a step T0, data alpha and beta are transferred to work registers 31 and 32. In a step T1, data alpha and beta are operated in an arithmetic logic unit 3. In a step T2, an operation result delta is stored in a general register 11, and simultaneously, data delta before the execution of the instruction is held in a corresopnding storage element 21 of a register contents holding device 2. In a step T3, the operation result is checked. Operation results in steps T4 and T5 are stored only in an operation register device 1. Data delta before the execution in the storage element 21 is inputted to an AND circuit 7 by research of a flag bit 21F. Operations of the logic unit 3 and the register device 1 are interrupted. Data delta is returned into the general register 11.
申请公布号 JPS57161948(A) 申请公布日期 1982.10.05
申请号 JP19810046357 申请日期 1981.03.31
申请人 FUJITSU KK 发明人 MARUO AKIHIRO;MIYAJIMA SHIGERU
分类号 G06F9/22;G06F9/30;G06F11/14 主分类号 G06F9/22
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