PROCEDE ET DISPOSITIF DE CONTROLE DES ENTREES D'UN PROCESSEUR DE SECURITE

摘要

A test unit (1FT) supplies a third logic state on the control lines (C1-5) via resistors (R) in the test lines (LT1-5). This logic state is midway between the logic o and logic 1 voltage levels. The resistors form voltage dividers with other resistors (R') in the addressing circuits to reduce the high addressing voltage by control of the test line (LT0) to the test unit. Coding circuits in the addressing circuits (A) verify if a particular control line is or is not selected. Buffers (1DD) between address demultiplexer (1FD) and the control lines provide independent shaping for the signals on each of the control lines. Thus a fault condition only affects one line. Simple faults are detected rapidly by the processor effecting the reading and test of the inputs at frequent intervals.