发明名称 VOLTAGE DECLINING CIRCUIT
摘要 PURPOSE:To decline a voltage in the state an input and an output are isolated without using a transformer by combining a plurality of capacitors and a switch. CONSTITUTION:When swithces S1, S2 are closed and switches S3-S6 are opened (during T1), capacitors C1, C2 are charged, and the terminal voltages of both the capacitors become equal. When switches S3-S6 are closed and switches S1, S2 are opened (during T2), the capacitors C1, C2are connected in parallel with the capacitor C3 through the switches S3, S6 and S4, S5. Because, two capacitors C1, C2 are connected in series between the input terminals 1a and 1b during T1, the voltage of 1/2 of the DC voltage V0 applied between the input terminals can be obtained at the respective capacitors, and accordingly the voltage of V0/2 can be obtained between the output terminals 2a and 2b during T2.
申请公布号 JPS57135678(A) 申请公布日期 1982.08.21
申请号 JP19810019258 申请日期 1981.02.12
申请人 MIYAZAKI TAKAHARU 发明人 MIYAZAKI TAKAHARU
分类号 H02M3/07;(IPC1-7):02M3/06 主分类号 H02M3/07
代理机构 代理人
主权项
地址