| 摘要 |
PURPOSE:To omit the rectifying and smoothing circuit in the output side to simplify the circuit constitution, by applying an input signal to a pulse transformer after making the input signal into pulses by clock pulses and by taking out an output signal through a latch circuit. CONSTITUTION:Clock pulses CLKA are applied to NAND gates 8-1-8-n to which input signals Si1-Sin are applied, and the clock pulse CLKA is gated by the width of each input signal and is applied to pulse transformers 2-1-2-n. A clock pulse CLKB which is slightly later than the clock pulse CLKA is applied to a pulse transformer 2-n+1 through an NAND gate 8-n+1. Outputs of transformers 2-1-2-n are applied to a register 7 of a parallel mode, and the output of the transformer 2-n+1 is applied to the clock terminal of the register 7, thus obtaining outputs So1-Son. |
