| 摘要 |
PURPOSE:To economize an information process system, by providing only a set of parity checking circuits which is used for information transferred via the common bus to a common bus. CONSTITUTION:A parity check code data d' to which a parity bit P is added by a parity generating circuit PG is transmitted to a common bus BUS. Then the data d' is transmitted to main memory devices MM1' and MM2', an external storage control part FDC plus data receiving circuits RD1-RD4 provided at an input/output control part TPC as well as to a parity checking circuit PC. The circuit PC carries out the parity check to the data d' and delivers the result of check in the form of a parity check output ck. Each device and circuit discriminate the effectiveness or ineffectiveness of the data d' received from the bus BUS by the output ck to start the discrimination of the address and other processes. |
