发明名称 PROCESSING DEVICE
摘要 PURPOSE:To simplify an entire processing device, by fixing a specific address line to a specific level at the state that the supply line is opened, in a processor of which sub-storage section is in removable state. CONSTITUTION:When a sub-storage unit 21 is fitted, the level of address lines 9-12 is determined with signal lines 9'-12', and when a jump instruction JMP6 of a program in a main storage 1 is executed, normal jumping of sub-storage section to an address 6 is excuted. When a sub-storage unit is removed, the signal line 9 is opened and the address line 9 is pulled up with a fixed circuit 4 and fixed to the level 1. When the jump instruction JMP6 is executed, the address jumped to an address 6 in the address space of the main storage 1.
申请公布号 JPS57114959(A) 申请公布日期 1982.07.17
申请号 JP19810001255 申请日期 1981.01.09
申请人 HITACHI SEISAKUSHO KK 发明人 MAEHARA TOMOHARU
分类号 G11C5/00;G06F12/06 主分类号 G11C5/00
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