发明名称 METHOD AND CIRCUIT OF CHECK BIT GENERATION
摘要 PURPOSE:To simplify a check bit generating circuit, by giving periodicity in block unit to an H matrix, and obtaining a check bit from an information bit split and sequentially applied by each block. CONSTITUTION:For example, information bits I1-I32 are split into 4 blocks B1-B4 of one word 8-bit to constitute an H matrix MX and a specified periodicity is given in the block unit of HMX. The 1st 8th column of information bits of each block of the HMX are applied to input terminals b1-b8 of a logical circuit group 10 consisting of trees of EX-OR, and the output of the circuit group 10 is inputted to a register group 20 via an EX-OR gate group 30. The gate group 30 takes exclusive logical sum of outputs between the circuit group 10 and register group 20 and the result is applied to the register group 20 again. The exculsive logical sum of all the inputs of the circuit group 10 and the logical product of control signals C4-C7 constitute the output of a control gate group 40 and the output is applied to gates 34-37 to output the check bits C1- C7 from the register group 20.
申请公布号 JPS57114953(A) 申请公布日期 1982.07.17
申请号 JP19810001190 申请日期 1981.01.09
申请人 TOKYO SHIBAURA DENKI KK 发明人 TANAKA NORIYUKI
分类号 G06F11/10;G06F12/16;H03M13/19 主分类号 G06F11/10
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