发明名称 DOT INTERFERENCE REDUCTION CIRCUIT
摘要 PURPOSE:To reduce dot interference without deterioration resolution, by rejecting chroma signal components through the operation of them only the period of existence, for the chrominance signal components remained not cancelled in luminance components. CONSTITUTION:A delay device 1 delaying a composite video input signal of NTSC system by 1H period, and a chrominance signal processing circuit 5 and the like are provided. Assuming that no chroma signal is present on the n-th horizontal scanning line and the chroma signal appears on the n+1-th horizontal scanning line. In this case, although no chroma signal is in existence in an output signal (d) of the circuit 1 at the n+1-th scanning period, since the chroma signal component is present in an input signal (a), this chroma signal component is applied to the base of a transistor TR30. The emitter voltage of a TR4 is increased every time the chroma signal component appears for the output, and the gain to the luminance signal component is reduced. Thus, the luminance signal component without chroma signal component is supplied to the circuit 5.
申请公布号 JPS57113686(A) 申请公布日期 1982.07.15
申请号 JP19810000506 申请日期 1981.01.07
申请人 HITACHI SEISAKUSHO KK 发明人 TAKEGAMI SHIGERU
分类号 H04N9/78;H04N9/64 主分类号 H04N9/78
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