| 摘要 |
A metal-oxide-semiconductor (MOS) structure and method for its fabrication wherein all contact hole locations are simultaneously photolithographically defined in the gate oxide layer and openings are etched at these locations prior to the deposition of polysilicon, which is then etched to form interconnections and contacts. The completed structure contains a thick oxide layer which forms an insulating dielectric which surrounds and is self-aligned with the contact holes and obviates the need for the commonly used intermediate layer of phosphosilicate glass. The width of the polysilicon contacts to sources and drains is less than the width of the active channel formed in a conventional n-channel silicon gate Metal-Oxide-Silicon field-effect transistor so that significant misalignment in the channel length direction between the opening in the gate oxide at a contact hole location and the polysilicon pattern will not cause failure of individual field effect transistors (FETs). Thus, any non-etched gate oxide which remains under the polysilicon contacts will mask against diffusion of impurities, but will not block the flow of current between source and drain of the FET because the polysilicon source or drain contact does not extend across the entire channel width, thereby providing parallel current paths.
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