| 摘要 |
PURPOSE:To realize a microprogram controller which has the extremely reduced number of steps of a program, by producing a corresponding synchronous command concurrently with a hardware processing request and utilizing the result of the hardware process of 2 machine cycles at the next step. CONSTITUTION:For a hardware process and a synchronous command of a microprogram, the read address of a microprogram storage memory 11 is designated by a maicroprogram address register 12 or a microprogram read register 13. Then a microinstruction word of the memory 11 is held at the register 13 to indicate a hardware operation. On the other hand, the indication of a microinstruction word is detected by a decoder 17. Then the machine cycle number is set to a register 18 in case the plural machine cycle process hardware synchronization is indicated. The replacement of the register 13 is suppressed by a decrementer 19 until a synchronization queuing register 18 reaches ''0'' to obtain synchronization. |
