| 摘要 |
<p>PURPOSE:To execute a smooth synchronizing operation when the synchronizing signal is detected again, by generating an artificial synchronizing signal for drop-out of the synchronizing signal. CONSTITUTION:A block B extracts the synchronizing signal from an information signal T and gives it to a phase comparing circuit 1 as a reference signal of the PLL circuit of a block A. A signal which is synchronized with the phase of the synchronizing signal and has a frequency of an integral multiple of the frequency of the synchronizing signal is obtained from the block A. This obtained signal is supplied to a block C which adds an artificial synchronizing signal. If the synchronizing signal is dropped out from the information signal T, a flip-flop 12 is not set, and therefore, a shift register 9 is not reset and continues the shift operation. Consequently, an output shifted from the regular synchronizing signal by a desired clock is given from the shift register 9 to an OR gate 15. When the regular synchronizing signal is given again, the shift register is reset, and the circuit is synchronized with the synchronizing signal immediately.</p> |
