| 摘要 |
PURPOSE:To access a memory at a high speed and to increase the operation speed of a CPU by exercising control by providing two systems of timing gener- ating circuits to a memory access controller. CONSTITUTION:The memory refreshment request control part 10 of a timing generation part T provided in a memory access controller MAC receives a memory request signal MA and an address signal AD from a bus AB. In addition, a main memory acces cycle MAC, a refreshment cycle MC, and an ROM cycle are generated. A timing generating circuit 14 receives the cycles MAC and RC through an OR gate OG and is actuated by the early one to generate a memory control signal S1. A timing generating circuit 16, on the other hand, responds to a momory request signal and is actuated all the time at its rise part to generate a cash memory, ROM and bus control signal S2. |
