A logic performing cell for use in array structures.

摘要

A logic performing cell for use in array structures is provided which allows greater density fabrication in integrated circuits and reduces operational delays. The array has a plurality of output lines intercepted by a plurality of orthogonally oriented input lines (I1, I2, ..., IN). Elements (T1, T2, ..., TN) in the form of a three terminal device are located at each of the intersections of the input and output lines so that logical functions are performed on interrogation signals placed on the input lines and the responses thereto placed on the output lines. The three terminal device transfer gates (T1, T2, ..., TN) are connected in groups of series strings (50, 51) which are connected in parallel to a recombination line. These groups of series connected transfer gates (T1, ...; T (N/2 + 1), ...) comprise a programmed mix of enhancement and depletion devices. Each logic function of each group of transfer gates (T1, ...; T(N/2 + 1) ...) establishes an output which, when coupled to the recombining output circuit line, provides an overall logic function for the logic performing cell.