发明名称 PHASE SYNCHRONIZING CIRCUIT
摘要 <p>PURPOSE:To constitute an error operating circuit with low-speed elements by operating an error only with a digital signal outputted in every period of color subcarrier wave. CONSTITUTION:A closed loop composed of an A/D converter 11, a burst extracting circuit 14, a pedestal level generator 41, a pedestal level error operation circuit 40, a D/A converter 42, a loop filter 43, and an analog adder 44 constitutes a control circuit to clamp the pedestal level of a composite color television signal so as to consist with a targeted value from the pedestal level generator 41, clamping the pedestal level digitally. An error operated by the error operating circuit 45 is applied to the control terminal of a voltage control oscillator 18 through a D/A converter 16 and a loop filter 17.</p>
申请公布号 JPS5773584(A) 申请公布日期 1982.05.08
申请号 JP19800149350 申请日期 1980.10.27
申请人 TOKYO SHIBAURA DENKI KK 发明人 KATOU MASAAKI;OGI KEISUKE
分类号 H04N11/04;H04N9/44 主分类号 H04N11/04
代理机构 代理人
主权项
地址
您可能感兴趣的专利