| 摘要 |
PURPOSE:To obtain a circuit which is capable of reducing the power consumption in case of a holding mode without givng a hindrance to operation of a dynamic circuit, by changeover a clock to the dynamic circuit, to a low speed clock in accordance with a holding or regular mode. CONSTITUTION:When a holding mode signal becomes a high level and a hoding mode is selected, AND gates 24, 26 of a clock selecting circuit 23 are opened and closed, respectively, by the holding mode signal and the holding mode signal through an inverter 25. Subsequently, a clock applied to a dynamic shift register 28 from an NOR circuit 27 is charged over from a high speed clock to a low speed clock passing through a frequency divider 22, and its operating speed is lowered, but the register 28 is operated exactly by small power consumption. Also, a timing signal is not generated from a timing generator 29 by a high level holding mode signal, a static circuit is not operated, and the power consumption is reduced. In this way, it is possible to obtain a circuit which is capable of reducing the power consumption in case of a holding mode without giving a hindrance to operation of a dynamic circuit. |
