| 摘要 |
<p>PURPOSE:To shorten a test time, by programming plural memory cells at the same time as to 1 bit of an output of a cell array. CONSTITUTION:In case of testing whether all cells of a non-volatile memory 1 are capable of writing or not, both signals Y1, Y2 of an additional circuit 14 are raised to the vicinity of potential of program power supply VP, and row wires 20, 21... are connected to the power supply VP. In this state, when voltage of 25V is applied in order to select 1 line wire each by a line decoder 4, potential of VP and potential of VP-Vth5 (Vth5 denotes threshold voltage of IG-FETs 50, 51...) are applied to the gate and the drain, respectively, of each IG-FET connected to its line wire, and write is executed. Accordingly, when writing in order to test a memory, the number of times corresponding to the number of line wires will do, and a test time is shortened.</p> |
