Microprocessor-controlled frequency synthesizer

摘要

A microprocessor-controlled synthesizer has a low frequency section producing a first output frequency and a comb loop producing a second output frequency. The comb loop includes a multiplier which produces harmonics of 100 MHz one of which is selected and fed to a mixer in a phase-locked loop having a variable divider, the other input of the mixer being a VCO output frequency. At low values of the second output frequency, the phase detector locks to the difference output from the mixer, at higher values to the sum output. The output from the mixer is mixed in a second mixer with the output of a further VCO, and a second phase detector selects the sum output from the second mixer to cover the first half of each decade of MHz and selects the difference output to cover the second half of the decade.