发明名称 CONTROL SIGNAL GENERATING CIRCUIT
摘要 PURPOSE:To simplify the constitution of hardware by obtaining a control signal by controlling the counting operation of a counter by the output of a flip-flop (FF) and by decoding the counter output. CONSTITUTION:When a set signal is applied to an FF1 and FF1 is set, a gate 3 is opened to apply a clock pulse from a reference clock generator to a counter 4. The count contents of the counter 4 are applied to a decoder circuit 5 to obtain desired control signals from terminals 0'15 successively. When the FF1 is reset, the control signals are ceased. This is effective when a controlled system is controlled cyclically.
申请公布号 JPS5744329(A) 申请公布日期 1982.03.12
申请号 JP19800119437 申请日期 1980.08.29
申请人 MEIDENSHA KK 发明人 SENOO TOSHIYA
分类号 H03K5/15 主分类号 H03K5/15
代理机构 代理人
主权项
地址