| 摘要 |
PURPOSE:To prevent the occurrence of a deadlock, by installing a sequence deciding circuit within an arithmetic processor having the highest priority and at the same time providing a synchronous process request line and a synchronous reply line independently. CONSTITUTION:A sequence deciding circuit 5 is provided to an arithmetic device BPU1 having the highest priority, and synchronous reply lines 201-212 are provided independently from synchronous process request lines 101-111 as the synchronous interface lines. The circuit 5 decides the accepting sequence of the request according to the priority when the synchronous process request is given from the BPU. On the other hand, BPU2-4 deliver first the synchronous process request to the circuit 5 when the synchronous process is required, delivers the synchronous request to all other BPUs when receiving the synchronous reply from the circuit 5 and starts the synchronous process when receiving the synchronous reply. As a result, the system is prevented from the occurrence of deadlock. |
