发明名称 FREQUENCY DIVIDING CIRCUIT
摘要 PURPOSE:To guarantee correct operation, by connecting a plurality of T-FFs with a reset terminal in cascade, applying an output of the T-FFs to a D-FF to which clocks of opposite polarity are applied, and resetting the T-FFs with the output of the D-FF. CONSTITUTION:When an output of a T-FF9 is at H, if the ouput of a T-FF7 is at H, a D-FF11 is set with a fall of the clock at a terminal (b), the potential of a terminal Q' is at L, and the T-FFs 7-9 are reset. As a result, the output of a gate 10 is at L and the D-FF is reset. That is, since the reset signal for the T-FF has sufficient length, the malfunction due to the fluctuation of FFs in manufacture can be prevented and accurate 1/6 frequency division can be assured.
申请公布号 JPS5735423(A) 申请公布日期 1982.02.26
申请号 JP19800110569 申请日期 1980.08.11
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SHIOTANI YUUICHI
分类号 H03K23/58;H03K23/00 主分类号 H03K23/58
代理机构 代理人
主权项
地址