发明名称 COMPUTER SYSTEM
摘要 PURPOSE:To simplify the constitution of a controller without lowering the reliability, by collating the outputs of two control arithmetic parts incorporating an automatic hard monitor device and carrying out a single system operation in case a fault is detected and then an operation of the status quo in case no coincidence is obtained through the collation, respectively. CONSTITUTION:CPUs 1 and 2 exchange mutually the arithmetic results through a data transfer bus 9 after the end of an operation and then carry out a collation and decision each. Then the gate of an output module 8 of the CPU side and selected by a selecting circuit 7 only when coincidence is obtained through the above collation. Thus the result of operation is transmitted to an external register 5'. In case no coincidence is obtained, an output of the result of operation is discontinued to the module 8 and at the same time the circuit 7 blocks the gate to ensure an operation of the status quo for the machinery at the working filed. On the other hand, in case a fault is detected by an automatic hard monitor functions incorporated to the CPUs 1 and 2, a CPU down-signal 11 is delivered. Then the operation is changed to the single system operation mode, and thus the operation is carried out with a single system without performing a collation and decision.
申请公布号 JPS5720847(A) 申请公布日期 1982.02.03
申请号 JP19800094035 申请日期 1980.07.11
申请人 HITACHI LTD 发明人 HAYAKAWA HIROHISA;KANZAKI HIDEO;SUGISAKA HIROSHI;MIZOGUCHI TSUYOSHI;AOTSU HIROAKI
分类号 G06F11/18;G06F11/16 主分类号 G06F11/18
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