发明名称 HIGH-SPEED SUBTRACTING CIRCUIT
摘要 PURPOSE:To realize a high-speed subtraction with just a pass through an adding circuit, by using a comparator for a subtracting process of two numbers showing the binary numbers. CONSTITUTION:A binary number A comprising A0, A1-AN is compared with a binary number B comprising B0, B1-BN. In this case, the output of a comparator is set at level ''0'' and ''1'' with A<B and A>B, respectively. In the case of A>B, a carry input CIN is at ''1'', and accordingly, the output S of an adding circuit is denoted by S=A+B'+1. Since the output of an inverter INV is at ''0'', the subtraction value D is denoted by D=S. Then the output S goes to S=A+B' because the input CIN is at ''0'' in A<B. At the same time, D=S' is satisfied since the output of the INV is at ''1''.
申请公布号 JPS5720843(A) 申请公布日期 1982.02.03
申请号 JP19800096047 申请日期 1980.07.14
申请人 NIPPON ELECTRIC CO 发明人 TSUJIMURA HIDEYUKI
分类号 G06F7/50;G06F7/505;G06F7/508 主分类号 G06F7/50
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