DIGITAL CLOCK RECOVERY CIRCUIT

摘要

DIGITAL CLOCK RECOVERY CIRCUIT A digital clock recovery circuit in which the phase of the divider chain driven by a local clock is controlled in order to maintain its output (the recovered clock signal) in synchronization with the incoming data stream. Additional control circuitry is included to inhibit phase correction when the relative phase of the two signals is within certain limits. Also phase correction takes place only after several indications one signal is leading or lagging the other, to prevent any correction due to noise. - i