| 摘要 |
<p>A semiconductor memory decoder (10) includes an OR gate (12) which receives a multi-bit memory address. A node (26) is precharged to a low state and driven to a high state when the OR gate (12) is not selected by the address. A node (34) is precharged to a high state and pulled to ground when the node (26) is driven to a high state. The high state precharged on the node (34) is conveyed to anode (40) which is connected to the gate terminal of a row driver transistor (54) and to a node (46) which is connected to the gate terminal of a row driver transistor (64). The one of the nodes (40, 46) not connected to a selected row line is isolated from the node (34) to render conductive the corresponding nonselected row driver transistor (54, 64). A high voltage state row driver signal (RD0, RD1) is transmitted through the selected row driver transistor (54, 64) to charge the selected row line (56, 66). A low voltage state row driver signal is transmitted through the nonselected row driver transistor (54, 64) to hold the nonselected row line at ground. </p> |
