Dynamic MOS memory store access controller - allows asynchronous processor and memory read and write cycles so that no processing time is lost by satisfying memory control constraints

摘要

The system allows a processor to operate asynchronously w.r.t. its memory making use of cycle request, read request and write request control signals to access the memory with a cycle time independent of the memory refresh cycle times. When the write request and cycle request are raised at the same time the write cycle is started as soon as the request has been latched by the memory. If the cycle request is raised alone, a read cycle is initiated and a write permit signal sent to the processor. The cycle is completed by a read request from the processor, whether or not the data is used. If, whilst the write permit signal is present, the processor produces a write request then a normal memory write cycle is executed. If after the write permit signal has been removed but within the cycle a write request is generated a second type of write cycle is executed within the processor cycle.