| 摘要 |
PURPOSE:To prevent the malfunction of devices owing to hardware faults by deciding whether the phase difference between the clock signals of different phases is normal or not. CONSTITUTION:The 1st clock 101 is inputted to a leading edge differentiating circuit 11 including a delay circuit 1 of a delay time T, which in turn outputs a leading edge differentiated signal 104, so that a flip-flop 6 is set by the leading edge of the 1st clock 101. The trailing edge differentiated signal 106 of a pulse 102 is outputted by a trailing edge differentiating circuit 12 including a delay circuit 4 of a delay time T, thereby resetting the flip-flop 6. The output of the flip-flop 6 is inputted to analog comparators 9, 10. The other inputs of the analog comparators 9, 10 are the 1st clock 101 and its inverted signal, the 2nd clock 109 delayed by the time T than the 1st clock and its inverted signal. Hence, when the 2nd clock has no normal delay time T with respect to the 1st clock, the analog comparators 9, 10 do not put out outputs 111, 112. Hence, the case in which the phase difference between the clocks is not normal is checked, whereby hardware faults are prevented. |
