| 摘要 |
PURPOSE:To enable to control the bus use of many processors with a small number of bus signal lines, by weighting respective bus use request lines and by adding priority order to respective processors, in a multiprocessor system. CONSTITUTION:In a multiprocessor system where plural processors 1 and 2 are connected to the common bus in parallel, n-number bus use request lines BRQ1- BRQ5 for the common bus are provided, and combinations of r-number lines, in this example, 2 lines selected from n-number lines, in this example, 5 lines are assigned to respective processors, and respective bus use request lines given preliminarily to combinations are weighted, and priority levels 7 and 9 are added to respective processors 1 and 2 by combinations of r-number lines, in this example, 2 lines, and states of bus use request lines other than assigned those are monitored to make the common bus use of respective processors (1) and (2) possible according to priority order Consequently, the right of bus use of processors whose number is equal to the number of combinations nCr is controlled. |
